Display panel and display device

ABSTRACT

A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data-writing module, a driving module, and a compensation module. The data-writing module is configured to selectively provide a data signal for the driving module. The driving module includes a driving transistor and is configured to provide a driving current to the light-emitting element. The compensation module is configured to compensate a threshold voltage of the driving transistor. The driving transistor includes a source, a gate, an active layer, a first drain and a second drain. A first driving portion is arranged between the source and the first drain, and a second driving portion is arranged between the first drain and the second drain. A length of a channel region of the first driving portion is L1, and a length of a channel region of the second driving portion is L2.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 17/453,170,filed on Nov. 1, 2021, which claims the priority of Chinese patentapplication No. 202110280448.3, filed on Mar. 16, 2021, the entirety ofall of which is incorporated herein by their references.

FIELD

The present disclosure generally relates to the field of displaytechnology and, more particularly, relates to a display panel and adisplay device.

BACKGROUND

With the continuous development of display technology, emergingdisplay-related technologies continue to emerge. Self-luminous displaypanels such as an organic light-emitting diode (OLED) display panel anda micro light-emitting diode (micro LED) display panel, etc., havegradually been favored by consumers, and have become a research hotspot.

In the OLED display panel and the micro LED display panel, a pixelcircuit that provides a driving current for a light-emitting element isa crucial element. In the pixel circuit, a driving transistor generatesthe driving current, and is one of key components. On the one hand, thedriving transistor needs to have desired driving capability, and on theother hand, the driving transistor needs to avoid generating signalerror when the display panel switches a screen to the greatest extent,to ensure that the generated driving current is as accurate as possible,and to ensure the display effect of the display panel. Therefore, how toreduce the signal error when the display panel switches the screen underthe premise of ensuring the driving capability of the driving transistoris an urgent technical problem that needs to be solved.

SUMMARY

One aspect of the present disclosure provides a display panel. Thedisplay panel includes a pixel circuit and a light-emitting element. Thepixel circuit includes a data-writing module, a driving module, and acompensation module. The data-writing module is configured toselectively provide a data signal for the driving module. The drivingmodule includes a driving transistor and is configured to provide adriving current to the light-emitting element. The compensation moduleis configured to compensate a threshold voltage of the drivingtransistor. The driving transistor includes a source, a gate, an activelayer, a first drain and a second drain. A first driving portion isarranged between the source and the first drain, and a second drivingportion is arranged between the first drain and the second drain. Alength of a channel region of the first driving portion is L1, and alength of a channel region of the second driving portion is L2. Thedata-writing module is connected to the source of the drivingtransistor, the compensation module is connected between the gate andthe first drain of the driving transistor, and L2/L1≥0.5, or thedata-writing module is connected to the first drain of the drivingtransistor, the compensation module is connected between the gate andthe second drain of the driving transistor, and L1/L2≥0.5.

Another aspect of the present disclosure provides a display device,including a display panel. The display panel includes a pixel circuitand a light-emitting element. The pixel circuit includes a data-writingmodule, a driving module, and a compensation module. The data-writingmodule is configured to selectively provide a data signal for thedriving module. The driving module includes a driving transistor and isconfigured to provide a driving current to the light-emitting element.The compensation module is configured to compensate a threshold voltageof the driving transistor. The driving transistor includes a source, agate, an active layer, a first drain and a second drain. A first drivingportion is arranged between the source and the first drain, and a seconddriving portion is arranged between the first drain and the seconddrain. A length of a channel region of the first driving portion is L1,and a length of a channel region of the second driving portion is L2.The data-writing module is connected to the source of the drivingtransistor, the compensation module is connected between the gate andthe first drain of the driving transistor, and L2/L1≥0.5, or thedata-writing module is connected to the first drain of the drivingtransistor, the compensation module is connected between the gate andthe second drain of the driving transistor, and L1/L2≥0.5.

Other aspects of the present disclosure can be understood by thoseskilled in the art in light of the description, the claims, and thedrawings of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

To more clearly illustrate the embodiments of the present disclosure,the drawings will be briefly described below. The drawings in thefollowing description are certain embodiments of the present disclosure,and other drawings may be obtained by a person of ordinary skill in theart in view of the drawings provided without creative efforts.

FIG. 1 illustrates a schematic diagram of a pixel circuit of anexemplary display panel consistent with disclosed embodiments of thepresent disclosure;

FIG. 2 illustrates a schematic diagram of a pixel circuit of anotherexemplary display panel consistent with disclosed embodiments of thepresent disclosure;

FIG. 3 illustrates a schematic diagram of a pixel circuit of anotherexemplary display panel consistent with disclosed embodiments of thepresent disclosure;

FIG. 4 illustrates a schematic diagram of a pixel circuit of anotherexemplary display panel consistent with disclosed embodiments of thepresent disclosure;

FIG. 5 illustrates a schematic cross-sectional view of a drivingtransistor consistent with disclosed embodiments of the presentdisclosure;

FIG. 6 illustrates a schematic cross-sectional view of another drivingtransistor consistent with disclosed embodiments of the presentdisclosure;

FIG. 7 illustrates a diagram of a relationship between brightness and aquantity of refreshed frames when a display panel refreshes a screen;

FIG. 8 illustrates a schematic diagram of a pixel circuit of anotherexemplary display panel consistent with disclosed embodiments of thepresent disclosure;

FIG. 9 illustrates a schematic diagram of a pixel circuit of anotherexemplary display panel consistent with disclosed embodiments of thepresent disclosure;

FIG. 10 illustrates a schematic cross-sectional view of another drivingtransistor consistent with disclosed embodiments of the presentdisclosure;

FIG. 11 illustrates a schematic top view of a driving transistorconsistent with disclosed embodiments of the present disclosure;

FIG. 12 illustrates a schematic top view of another driving transistorconsistent with disclosed embodiments of the present disclosure;

FIG. 13 illustrates a schematic diagram of a pixel circuit of anotherexemplary display panel consistent with disclosed embodiments of thepresent disclosure;

FIG. 14 illustrates a schematic diagram of a pixel circuit of anotherexemplary display panel consistent with disclosed embodiments of thepresent disclosure; and

FIG. 15 illustrates a schematic diagram of an exemplary display deviceconsistent with disclosed embodiments of the present disclosure.

DETAILED DESCRIPTION OF THE DISCLOSURE

Reference will now be made in detail to exemplary embodiments of thedisclosure, which are illustrated in the accompanying drawings. Whereverpossible, the same reference numbers will be used throughout thedrawings to refer to the same or the alike parts. The describedembodiments are some but not all of the embodiments of the presentdisclosure. Based on the disclosed embodiments, persons of ordinaryskill in the art may derive other embodiments consistent with thepresent disclosure, all of which are within the scope of the presentdisclosure.

Similar reference numbers and letters represent similar terms in thefollowing Figures, such that once an item is defined in one Figure, itdoes not need to be further discussed in subsequent Figures.

The present disclosure provides a display panel. FIG. 1 illustrates aschematic diagram of a pixel circuit of a display panel consistent withdisclosed embodiments of the present disclosure; FIG. 2 illustrates aschematic diagram of a pixel circuit of another display panel consistentwith disclosed embodiments of the present disclosure; FIG. 3 illustratesa schematic diagram of a pixel circuit of another display panelconsistent with disclosed embodiments of the present disclosure; FIG. 4illustrates a schematic diagram of a pixel circuit of another displaypanel consistent with disclosed embodiments of the present disclosure;FIG. 5 illustrates a schematic cross-sectional view of a drivingtransistor consistent with disclosed embodiments of the presentdisclosure; and FIG. 6 illustrates a schematic cross-sectional view ofanother driving transistor consistent with disclosed embodiments of thepresent disclosure.

Referring to FIGS. 1-6 , the display panel may include a pixel circuit10 and a light-emitting element 20. The pixel circuit 10 may include adata-writing module 11, a driving module 12, and a compensation module13. The data-writing module 11 may be configured to selectively providea data signal for the driving module 12. The driving module 12 may beconfigured to provide a driving current for the light-emitting element20, and the driving module 12 may include a driving transistor TO. Thecompensation module 13 may be configured to compensate a thresholdvoltage of the driving transistor T0. The driving transistor T0 mayinclude a source 102 (node N2), a gate 101 (node N1), an active layer105, a first drain 103 (node N3) and a second drain 104 (node N4). Afirst driving portion T01 may be disposed between the source 102 and thefirst drain 103, and a second driving portion T02 may be disposedbetween the first drain 103 and the second drain 104. A length of achannel region of the first driving portion T01 may be L1, and a lengthof a channel region of the second driving portion T02 may be L2.

In one embodiment, referring to FIG. 1 and FIG. 2 , the data-writingmodule 11 may be connected to the source 102, and the compensationmodule 13 may be connected between the gate 101 and the first drain 103.In another embodiment, referring to FIG. 3 and FIG. 4 , the data-writingmodule 11 may be connected to the first drain 103, and the compensationmodule 13 may be connected between the gate 101 and the second drain104. For the pixel circuit associated with FIGS. 1-2 ,L2/L1≥ΔVsd2/(ΔVsg+V0)−1 and 0≤V0≤ΔVgd2×½; alternatively, for the pixelcircuit associated with FIGS. 3-4 , L1/L2≥ΔVsd2/(ΔVgd2+V0)−1 and0≤V0≤ΔVsg×½, where ΔVsd2=|Vs−Vd2|, ΔVsg=|Vs−Vg|, and ΔVgd2=|Vg-Vd2|. Ina light-emitting stage of the light-emitting element 20, Vs may be avoltage of the source of the driving transistor, Vd2 may be a voltage ofthe second drain of the driving transistor, and Vg may be a voltage ofthe gate of the driving transistor.

Referring to FIG. 5 and FIG. 6 , in a light-emitting stage of thelight-emitting element 20, because the driving transistor T0 generates adriving current for the light-emitting element 20 in the light-emittingstage, the gate 101 of the driving transistor T0 may store a data signalrequired for emitting light. The transistor may often operate in anunsaturated state, the voltages of the source 102 and the second drain104 may not be equal, and the voltage difference may be substantiallylarge. In view of this, the voltage difference between the gate 101 andthe source 102 may not be equal to and may be significantly differentfrom the voltage difference between the gate 101 and the second drain104. When the voltage difference between the gate 101 and the source 102is significantly different from the voltage difference between the gate101 and the second drain 104, for the side with a larger voltagedifference, because the electric field is strong, carriers may migrateunder the action of the strong electric field, and may be easily trappedby defects to form a built-in electric field and generate polarization.Such phenomenon may cause the Vd-Ig curve of the driving transistor T0to be deviated, and may cause a deviation of a threshold voltage. Forexample, when the threshold voltage of the driving transistor T0 is Vthand the deviation is ΔV, the deviated threshold voltage may be Vth±ΔV.

It should be noted that arrows in FIG. 5 and FIG. 6 may indicate thedensity of electric field lines between the source and the gate, betweenthe first drain and the gate, and between the second drain and the gate.The density of the electric field lines may exemplarily illustrate thestrength of the electric field, and directions of the arrows may beadjusted according to the specific situation.

FIG. 7 illustrates a diagram of a relationship between brightness and aquantity of refreshed frames when a display panel refreshes a screen,where the ordinate may be the brightness of the light-emitting element20, and the abscissa may be the quantity of the refreshed frames.Referring to FIG. 7 , the starting point may stands starting from ascreen with a substantially small driving current (referred to a blackscreen, which may actually be a light-emitting stage with asubstantially small light-emitting current), and the brightness at thestarting point may be close to 0. When refreshing the screen, theexpected brightness may be 450 nits. After the first frame data isrefreshed, the actual brightness may first reach 300 nits and then maydrop to a certain extent, and, thus, may not reach the expectedbrightness.

When the screen is switched, due to the deviation of the thresholdvoltage of the driving transistor in the previous light-emitting period,the threshold voltage of the driving transistor may be deviated toVth±ΔV. In a data-writing stage, the deviation of the threshold voltagemay cause the data signal Vdata written to the gate of the drivingtransistor to be unstable, and Vdata may not reach an accurate value,such that after the first frame is refreshed, the actual brightness maynot reach the expected brightness.

When the second frame data is refreshed, the actual brightness may firstreach 450 nits, while may drop to a certain extent. When the secondframe data is refreshed, the voltages of the source, the gate, and thedrain of the driving transistor in the light-emitting stage may bechanged in the data-writing stage. The deviation of the thresholdvoltage ΔV may be gradually improved by writing data twice, and, thus,ΔV may become smaller and smaller, and the threshold voltage may tend tobe stabilized. With respect to refreshing the first frame data, whenrefreshing the second frame data, the data signal Vdata may be moreaccurate, and the actual brightness may be close to a target brightness.When the third frame data is refreshed, the deviation of the thresholdvoltage may be further improved, and, thus, ΔV may become smaller andsmaller, the threshold voltage may be stabilized, the written datasignal Vdata may be substantially accurate, and the actual brightnessmay be substantially close to the target brightness. After refreshingdata multiple times, the brightness may gradually reach the targetbrightness.

However, when the quantity of refreshed frames is substantially large,eye may perceive the brightness change, which may cause a flickeringproblem when switching the display screen. Therefore, the quantity ofrefreshed frames required to reach the target brightness may need to bereduced as much as possible. The quantity of refreshed frames may berelated to the deviation of the threshold voltage of the drivingtransistor, and the smaller the deviation of the threshold voltage ΔV,the easier the brightness reaching the target brightness.

The voltage difference between the gate 101 and the source 102 may besignificantly different from the voltage difference between the gate 101and the second drain 104, which may be one of main reasons that causethe deviation of the threshold voltage ΔV. Therefore, in the presentdisclosure, the driving transistor T0 may be divided into two portions:the first driving portion T01 and the second driving portion T02. Amongthe first driving portion T01 and the second driving portion T02,whoever of the first driving portion T01 or the second driving portionT02 has a larger voltage difference, causes the deviation of thethreshold voltage, and causes the unstable written data signal, may notbe connected in the data-writing stage, and whoever of the first drivingportion T01 or the second driving portion T02 has a smaller voltagedifference may be connected, which may improve the accuracy of thewritten data signal as much as possible.

In the light-emitting stage of the light-emitting element 20, when thevoltage difference between the first drain 103 and the gate 101 is lessthan a certain voltage value V0, where 0≤V0≤ΔVgd2×½ or 0≤V0≤ΔVsg×½, inother words, when the voltage difference between the first drain 103 andthe gate 101 is reduced to half of the voltage difference between thegate 101 and the second drain 104, or half of the voltage differencebetween the gate 101 and the source 102, the portion with a greaterelectric field strength may not participate in the data-writing stage,to ensure that the expected brightness may be reached as soon aspossible when refreshing the screen.

Therefore, in the present disclosure, the driving transistor T0 may bedivided into two portions: the first driving portion T01 and the seconddriving portion T02. The first driving portion T01 may be a portionbetween the source 102 and the first drain 103, and the second drivingportion T02 may be a portion between the first drain 103 and the seconddrain 104. The length of the channel region of the first driving portionT01 may be L1, and the length of the channel region of the seconddriving portion T02 may be L2. When the voltage difference between thefirst drain 103 and the gate 101 is less than the certain voltage valueV0, i.e., when |Vg−Vd1|≤V0, Vg−V0≤Vd1≤Vg+V0.

Referring to FIG. 1 and FIG. 2 , when the first driving portion isselected to participate in the data-writing stage, the data-writingmodule 11 may be connected to the source 102, and the compensationmodule 13 may be connected between the gate 101 and the first drain 103.Because |Vs−Vd1|≈|Vs−Vd2|×L1/(L1+L2), when Vs≥Vd1,(Vs−Vg)−V0=Vs−(Vg+V0)≤Vs−Vd1=|Vs−Vd1|≤Vs−(Vg−V0)=(Vs−Vg)+V0; or whenVs≤Vd1, (Vg−Vs)−V0=Vg−V0−Vs≤Vd1−Vs=|Vs−Vd1|≤Vg−Vs+V0=(Vg−Vs)+V0. Because(Vs−Vg)|Vs−Vg| and (Vg−Vs)≤|Vs−Vg|, |Vs−Vd1|≤|Vs−Vg|+V0, in other words,|Vs−Vd2|×L1/(L1+L2)≤|Vs−Vg|+V0. Therefore,L2/L1≥|Vs−Vd2|/[|Vs−Vg|+V0]−1=ΔVsd2/(ΔVsg+V0)−1.

According to the above calculation, the values of the lengths L1 and L2may affect the voltage difference between the first drain 103 and thegate 101. When L2/L1≥ΔVsd2/(ΔVsg+V0)−1 and 0≤V0≤ΔVgd2×½, it may beensured that the voltage difference between the gate 101 and the firstdrain 103 may be less than half of the voltage difference between thegate 101 and the second drain 104, which may avoid the problems wherethe inputted data signal is inaccurate and the brightness is difficultto reach the expected brightness when the screen is refreshed due to toolarge voltage difference between the gate 101 and the second drain 104.

Similarly, referring to FIG. 3 and FIG. 4 , when the second drivingportion is selected to participate in the data-writing stage, thedata-writing module 11 may be connected to the first drain 103, and thecompensation module 13 may be connected between the gate 101 and thesecond drain 104. Because |Vd2-Vd1|≈|Vs−Vd2|×L2/(L1+L2), when Vd2≥Vd1,(Vd2−Vg)−V0≤Vd2−(Vg+V0)≤Vd2−Vd1=|Vd2−Vd1|≤Vd2−(Vg−V0)=(Vd2−Vg)+V0; orwhen Vd2≤Vd1,(Vg−Vd2)−V0=(Vg−V0)−Vd2≤Vd1−Vd2=|Vd2−Vd1|≤(Vg+V0)−Vd2=(Vg−Vd2)+V0.Because (Vd2−Vg)≤|Vg−Vd2| and (Vg−Vd2)≤|Vg−Vd2|, Vd2−Vd1|≥|Vg−Vd2|+V0,in other words, |Vs−Vd2|×L2/(L1+L2)≤|Vg−Vd2|+V0. Therefore,L1/L2≥|Vs−Vd2|/[|Vg−Vd2|+V0]-1=ΔVsd2/(ΔVgd2+V0)−1.

According to the above calculation, the values of the lengths L1 and L2may affect the voltage difference between the first drain 103 and thegate 101. When L1/L2≥ΔVsd2/(ΔVgd2+V0)−1 and 0≤V0≤ΔVsg×½, it may beensured that the voltage difference between the gate 101 and the firstdrain 103 may be less than half of the voltage difference between thegate 101 and the source 102, which may avoid the problems where theinputted data signal is inaccurate and the brightness is difficult toreach the expected brightness when the screen is refreshed due to toolarge voltage difference between the gate 101 and the source 102.

The light-emitting stage of the light-emitting element defined in thepresent disclosure may be limited in terms of the circuit workingmechanism, which may not only include the light that is actually emittedfrom the light-emitting element and is capable of being recognized bythe human eye, but also include the black screen with substantiallysmall driving current and substantially low brightness.

In addition, in the present disclosure, in the pixel circuit 10, thenode N1 may be connected to the gate 101 of the driving transistor, thenode N2 may be connected to the source 102 of the driving transistor,the node N3 may be connected to the first drain 103 of the drivingtransistor, and the node N4 may be connected to the second drain 104 ofthe driving transistor. The first driving portion T01 and the seconddriving portion T02 may be two portions of the driving transistor T0,and may together form the driving transistor T0. In other words, thedriving transistor T0 may still be an integral transistor. Each of thegate 101 and the active layer 105 of the driving transistor T0 may bedisposed as one piece. The first drain 103 may be connected to theactive layer 105, and may be a node drawn from the middle of the drivingtransistor T0, and may be configured to be connect to the compensationmodule 13. The connection method of the first drain 103 may be analyzedin detail later. In practical applications, each of the gate 101 and theactive layer 105 of the driving transistor T0 may be divided intoseveral pieces. The present disclosure may mainly focus on the casewhere the driving transistor T0 is an integral transistor.

Optionally, in one embodiment, referring to FIG. 1 , the drivingtransistor T0 may be a PMOS transistor. The data-writing module 11 maybe connected to the source 102, the compensation module 13 may beconnected between the gate 101 and the first drain 103, andL2/L1≥ΔVsd2/(ΔVsg+V0)−1 and 0≤V0≤ΔVgd2×½. When the driving transistor T0is a PMOS transistor, in the light-emitting stage, the drivingtransistor T0 may be turned on, and the voltage of the gate 101 may beless than the voltage of the source 102. In the pixel circuitillustrated in FIG. 1 , in the light-emitting stage, the source voltageVs of the driving transistor T0 may be a PVDD signal, the gate voltageVg may be (Vdata-Vth), and the second drain voltage Vd2 may often be asubstantially low voltage, e.g., Vs=4.6V, Vg=3V, and Vd2=−2V. In view ofthis, the voltage difference between the gate voltage Vg and the seconddrain voltage Vd2 (ΔVgd2=|Vg−Vd2|) may be substantially large, forexample, ΔVgd2 may be 5V or even greater. The voltage difference betweenthe gate voltage Vg and the source voltage Vs (ΔVsg=|Vg−Vs|) may besubstantially small, for example, ΔVsg may be 1.5V or even smaller. Thesource voltage Vs may often be greater than the gate voltage Vg, and thegate voltage Vg may often be greater than the second drain voltage Vd2.

In view of this, the problem shown in FIG. 5 may occur. The arrows inFIG. 5 may illustrate densities of electric field lines between thesource and the gate, between the first drain and the gate, and betweenthe second drain and the gate, which may merely exemplarily illustratethe electric field strength through the density of the electric fieldlines. Because the difference between the source voltage Vs and the gatevoltage Vg is substantially small, the electric field strength betweenthe source and the gate may be substantially small. Because thedifference between the second drain voltage Vd2 and the gate voltage Vgis substantially large, the electric field strength between the seconddrain and the gate may be substantially large. As described above, thestrong electric field between the second drain and the gate may be themain reason that causes the deviation of the threshold voltage of thedriving transistor T0.

Therefore, for such driving transistor, the first driving portion T01may be selected to participate in the data-writing stage, while thesecond driving portion T02 may not participate in the data-writingstage, such that the deviation of the threshold voltage of the drivingtransistor T0 and the problem of inaccurate written data signal causedby the second driving portion T02 when the screen is refreshed may befully avoided. In view of this, L2/L1≥ΔVsd2/(ΔVsg+V0)−1, and0≤V0≤ΔVgd2×½. Because ΔVgd2 is substantially large, ΔVgd1 may be smallerthan ΔVgd2×½, such that the voltage difference between the gate 101 andthe first drain 103 may be reduced to within half of the voltagedifference between the gate 101 and the second drain 104, and the seconddriving portion T02 with a substantially large voltage difference maynot participate in the data-writing stage.

Optionally, in one embodiment, referring to FIG. 4 , the drivingtransistor T0 may be an NMOS transistor. The data-writing module 11 maybe connected to the first drain 103, the compensation module 13 may beconnected between the gate 101 and the second drain 104, andL1/L2≥ΔVsd2/(ΔVgd2+V0)−1, 0≤V0≤ΔVsg×½. When the driving transistor T0 isan NMOS transistor, in the light-emitting stage, the driving transistorT0 may be turned on, and the voltage of the gate 101 may be greater thanthe voltage of the source 102. In the pixel circuit illustrated in FIG.4 , in the light-emitting stage, the second drain voltage Vd2 of thedriving transistor T0 may be the PVDD signal, the gate voltage Vg may be(Vdata+Vth), and the source voltage Vs may be a substantially lowvoltage, e.g., Vd2=4.6V, Vg=4V, and Vs=1V. In view of this, the voltagedifference between the gate voltage Vg and the second drain voltage Vd2(ΔVgd2=|Vg−Vd2|) may be substantially small, for example, ΔVgd2 may be0.6V or even smaller. The voltage difference between the gate voltage Vgand the source voltage Vs (ΔVsg=|Vg−Vs|) may be substantially large, forexample, ΔVsg may be 3V or even greater.

In view of this, the problem shown in FIG. 6 may occur. The arrows inFIG. 6 may illustrate densities of electric field lines between thesource and the gate, between the first drain and the gate, and betweenthe second drain and the gate, which may merely exemplarily illustratethe intensity of the electric field through the density of the electricfield lines. Because the difference between the source voltage Vs andthe gate voltage Vg is substantially large, the electric field strengthbetween the source and the gate may be substantially large. As describedabove, the strong electric field between the source and the gate may bethe main reason that causes the deviation of the threshold voltage ofthe driving transistor T0.

Therefore, for such driving transistor, the second driving portion T02may be selected to participate in the data-writing stage, while thefirst driving portion T01 may not participate in the data-writing stage,such that the deviation of the threshold voltage of the drivingtransistor T0 and the problem of inaccurate written data signal causedby the first driving portion T01 when the screen is refreshed may befully avoided. In view of this, L1/L2≥ΔVsd2/(ΔVgd2+V0)−1, and0≤V0≤ΔVsg×½. Because ΔVsg is substantially large, ΔVgd1 may be smallerthan ΔVsg×½, such that the voltage difference between the gate 101 andthe first drain 103 may be reduced to within half of the voltagedifference between the gate 101 and the source 102, and the firstdriving portion T01 with a substantially large voltage difference maynot participate in the data-writing stage.

In addition, in certain embodiments, referring to FIG. 3 , the drivingtransistor T0 may be a PMOS transistor. The data-writing module 11 maybe connected to the first drain 103, the compensation module 13 may beconnected between the gate 101 and the second drain 104, andL1/L2≥ΔVsd2/(ΔVgd2+V0)−1 and 0≤V0≤ΔVsg×½. In view of this, in thelight-emitting stage, the driving transistor T0 may contain some specialdesigns, which may cause the difference between ΔVsg and ΔVgd2 to besubstantially small, or ΔVsg to be greater than ΔVgd2. In view of this,the electric field between the source and the gate may be the mainreason that causes the deviation of the threshold voltage of the drivingtransistor T0. Therefore, for such PMOS driving transistor, the seconddriving portion T02 may be selected to participate in the data-writingstage, while the first driving portion T01 may not participate in thedata-writing stage.

In certain embodiments, referring to FIG. 2 , the driving transistor T0may be an NMOS transistor. The data-writing module 11 may be connectedto the source 102, the compensation module 13 may be connected betweenthe gate 101 and the first drain 103, and L2/L1≥ΔVsd2/(ΔVsg+V0)−1 and0≤V0≤ΔVgd2×½. In view of this, in the light-emitting stage, the drivingtransistor T0 may contain some special designs, which may cause thedifference between ΔVsg and ΔVgd2 to be substantially small, or ΔVgd2 tobe greater than ΔVsg. In view of this, the electric field between thegate and the second drain may be the main reason that causes thedeviation of the threshold voltage of the driving transistor T0.Therefore, for such NMOS driving transistor, the first driving portionT01 may be selected to participate in the data-writing stage, while thesecond driving portion T02 may not participate in the data-writingstage.

Optionally, in certain embodiments, the data-writing module 11 may beconnected to the source 102, the compensation module 13 may be connectedbetween the gate 101 and the first drain 103, andL2/L1≥ΔVsd2/(ΔVsg+V0)−1 and 0≤V0≤ΔVgd2×½, where ΔVsd2≥ΔVsg+V0. In suchconnection mode, as described above, because the voltage differenceΔVgd2 between the gate 101 and the second drain 104 is oftensubstantially large, and the voltage difference ΔVsg between the gate101 and the source 102 is substantially small, the second drivingportion T02 may not be connected in the data-writing stage. Throughsetting ΔVsd2≥ΔVsg+V0, L2/L1≥0 may be ensured. Under such premise, theratio of L2/L1 may also have any other restriction, which may bedescribed later.

In certain embodiments, the data-writing module 11 may be connected tothe first drain 103, the compensation module 13 may be connected betweenthe gate 101 and the second drain 104, and L1/L2≥ΔVsd2/(ΔVgd2+V0)−1 and0≤V0≤ΔVsg×½, where ΔVsd2≥ΔVgd2+V0. In such connection mode, as describedabove, because the voltage difference ΔVsg between the gate 101 and thesource 102 is often substantially large, and the voltage differenceΔVgd2 between the gate 101 and the second drain 104 is substantiallysmall, the first driving portion T01 may not be connected in thedata-writing stage. Through setting ΔVsd2≥ΔVgd2+V0, L1/L2≥0 may beensured. Under such premise, the ratio of L1/L2 may also have any otherrestriction, which may be described later.

In one embodiment, optionally, the data-writing module 11 may beconnected to the source 102, the compensation module 13 may be connectedbetween the gate 101 and the first drain 103, and L2/L1≥ΔVsd2/V0−1 and0≤V0≤ΔVgd2×½. In a display panel, different light-emitting element 20may have different requirements for light-emitting current when emittinglight. For the pixel circuits in a same display panel, the gate voltagesVg of the driving transistors T0 in the light-emitting stage may bedifferent. Based on the limitations of the process, to fully simplifythe process, the pixel circuits in a same panel may be expected to befabricated uniformly, and the overall structures of the drivingtransistors of different pixel circuits may be basically the same. Whenthe Vg requirements are different while the basic structure requirementsof the driving transistors are basically the same, the formulaL2/L1≥ΔVsd2/(ΔVsg+V0)−1 may be further unified improved.

For the PMOS transistor, in such connection mode, the source voltage Vsmay often be a PVDD signal, which may be a high voltage signal. The gatevoltage Vg may often be lower than the source voltage Vs. When Vgapproaches Vs, the driving current may become smaller. When Vg≈Vs, ablack screen may occur, which may be reflected in the formulas asΔVsg≥0, ΔVsg+V0≥V0, and ΔVsd2/(ΔVsg+V0)≤ΔVsd2/V0. The limit of Vg≈Vs maybe taken as the standard, and L2/L1≥ΔVsd2/V0−1≥ΔVsd2/(ΔVsg+V0)−1 may bedefined. In view of this, any other case where Vg≤Vs may often meet therequirement of the range of L2/L1.

Similarly, for the NMOS transistor, to simplify the process, the drivingtransistors may be uniformly designed, and Vg may often be greater thanVs. When Vg≈Vs, the black screen may occur. The limit of Vg≈Vs may betaken as the standard, and L2/L1≥ΔVsd2/V0−1≥ΔVsd2/(ΔVsg+V0)−1 may bedefined. In view of this, any other case where Vg≤Vs may often meet therequirement of the range of L2/L1.

It should be noted that 0≤V0≤ΔVgd2×½ may be defined. Because both Vg andVd2 may be two variables in actual situations, and ΔVgd2 may also be avariable. In specific implementation, to uniformly design the pixelcircuits in the same display panel, V0 may be set to a certain valuewith a substantially small value, such that most or all situations mayfall within the above range as much as possible, to facilitate theunified design of the panel. The value of V0 may be further describedlater.

Optionally, in one embodiment, the data-writing module 11 may beconnected to the first drain 103, the compensation module 13 may beconnected between the gate 101 and the second drain 104, andL1/L2≥ΔVsd2/V0−1 and 0≤V0≤ΔVsg×½. Similarly, to simplify the process,when selecting L1/L2, considering the unified design of the drivingtransistors in the same display panel, the limit of ΔVgd2=0 may be takento obtain L1/L2≥ΔVsd2/V0−1≥ΔVsd2/(ΔVgd2+V0)−1, such that a unifieddesign of the driving transistors in the panel may be achieved. In viewof this, V0 may be set to a certain value with a substantially smallvalue, such that most or all situations may fall within the above rangeas much as possible, to facilitate the unified design of the panel. Thevalue of V0 may be further described later.

Optionally, in one embodiment, the data-writing module 11 may beconnected to the source 102, the compensation module 13 may be connectedbetween the gate 101 and the first drain 103, and L2/L1≥0.5. Asdescribed above, in such connection mode, L2/L1≥ΔVsd2/(ΔVsg+V0)−1 and0≤V0≤ΔVgd2×½. Such connection method may often be selected whenΔVgd2≥ΔVsg. Because for the PMOS transistor, Vd2≤Vg≤Vs, or for the NMOStransistor, Vs≤Vg≤Vd2, then ΔVsd2=ΔVsg+ΔVgd2. When ΔVsg≤ΔVgd2≤2≤ΔVsg,ΔVsg≥⅓×ΔVsd2. For example, Vs=4.6V, Vd2=−2V, ΔVsg≥⅓ 6.6V=2.2V, andΔVgd2≤⅔ 6.6V=4.4V. In view of this, the voltage difference between ΔVsgand Vsd2 may be approximately 2V.

When the voltage difference between ΔVsg and Vsd2 is within such range,the electric field strength between the gate 101 and the second drain104 may be substantially small to a certain extent, which may not causetoo much deviation of the threshold voltage of the driving transistor.When ΔVgd2≥2×ΔVsg, in other words, when ΔVgd2≥⅔×ΔVsd2, the voltagedifference between ΔVgd2 and ΔVsg may be substantially large, which maycause a substantially obvious deviation of the threshold voltage. Toavoid such phenomenon, in one embodiment, a partial region whereΔVgd2≥2×ΔVsg may not participate in the data-writing stage. In view ofthis, ΔVsg≤⅓×ΔVsd2, and ΔVgd2≥⅔×ΔVsd2. Further, V0≤⅔×ΔVsd2×½≤ΔVgd2×½ maybe defined, then, ΔVsg+V0≤⅓×ΔVsd2+⅔ ΔVsd2×½=⅔×ΔVsd2, therefore,L2/L1≥ΔVsd2/(ΔVsg+V0)−1≥Vsd2/(⅔×ΔVsd2)−1=0.5 may be obtained.

In view of this, when the voltage difference between the gate and thesecond drain is substantially large, the portion with a significantlylarge voltage difference may not participate in the data-writing stage,thereby facilitating to reduce the deviation of the threshold voltage ofthe driving transistor.

Alternatively, in one embodiment, the data-writing module 11 may beconnected to the first drain 103, the compensation module 13 may beconnected between the gate 101 and the second drain 104, and L1/L2≥0.5.Similarly, in such connection mode, L1/L2≥ΔVsd2/(ΔVgd2+V0)−1, and0≤V0≤ΔVsg×½. Such connection mode may often be selected when ΔVsg≥ΔVgd2.Because for the PMOS transistor, Vd2≤Vg≤Vs, or for the NMOS transistor,Vs≤Vg≤Vd2, then ΔVsd2=ΔVsg+ΔVgd2. When ΔVgd2≤ΔVsg≤2×ΔVgd2,ΔVgd2≥⅓×ΔVsd2, for example, Vs=−2V, Vd2=4.6V, ΔVgd2≥⅓×6.6V=2.2V, andΔVsg≤⅔×6.6V=4.4V. In view of this, the voltage difference between ΔVsgand Vsd2 may be approximately 2V.

When the voltage difference between ΔVsg and Vsd2 is within such range,the electric field strength between the gate 101 and the source 102 maybe substantially small to a certain extent, which may not cause too muchdeviation of the threshold voltage. When ΔVsg≥2×ΔVgd2, in other words,when ΔVsg≥⅔×ΔVsd2, the voltage difference between ΔVsg and ΔVgd2 may besubstantially large, which may cause a substantially obvious deviationof the threshold voltage. To avoid such phenomenon, in one embodiment, apartial region where ΔVsg≥2×ΔVgd2 may not participate in thedata-writing stage. In view of this, ΔVgd2≥⅓×ΔVsd2, and ΔVsg≥⅔×ΔVsd2.Further, V0≤⅔×ΔVsd2×½≤ΔVsg×½ may be defined, thenΔVgd2+V0≤⅓×ΔVsd2+⅔×ΔVsd2×½=⅔×ΔVsd2, therefore,L1/L2≥ΔVsd2/(ΔVgd2+V0)−1≥Vsd2/(⅔×ΔVsd2)−1=0.5 may be obtained.

In view of this, when the voltage difference between the gate and thesource is substantially large, the portion with a significantly largevoltage difference may not participate in the data-writing stage,thereby facilitating to reduce the deviation of the threshold voltage ofthe driving transistor.

In addition, optionally, as described above, to uniformly fabricate thedriving transistors of the display panel and to simplify the process,the data-writing module 11 may be connected to the source 102, thecompensation module 13 may be connected between the gate 101 and thefirst drain 103, and L2/L1≥ΔVsd2/V0−1 and 0≤V0≤ΔVgd2×½. In the case ofV0≤⅔×ΔVsd2×½=⅓×ΔVsd2, ΔVsd2/V0≥ΔVsd2/(⅓×ΔVsd2)=3 and L2/L1≥ΔVsd2/V0−1≥2.In view of this, while making the portion of the driving transistor witha significantly large voltage difference not participate in thedata-writing stage, the unified design of the panel may be facilitated,which may effectively simplify the process.

Optionally, as described above, to uniformly fabricate the drivingtransistors of the display panel and to simplify the process, thedata-writing module 11 may be connected to the first drain 103, thecompensation module 13 may be connected between the gate 101 and thesecond drain 104, and L1/L2≥ΔVsd2/V0−1, and 0≤V0≤ΔVsg×½. In the case ofV0≤⅔×ΔVsd2×½=⅓ ΔVsd2, ΔVsd2/V0≥ΔVsd2/(⅓×ΔVsd2)=3 and L1/L2≥ΔVsd2/V0−1≥2.In view of this, while making the portion of the driving transistor witha significantly large voltage difference not participate in thedata-writing stage, the unified design of the panel may be facilitated,which may effectively simplify the process.

In addition, optionally, in one embodiment, to ensure the voltagedifference ΔVgd1 between the gate voltage Vg and the first drain voltageVd1 to be further reduced, the range of V0 may be further reduced, whereV0≤ΔVgd2×⅓, or V0≤ΔVsg×⅓, which may facilitate to fully reduce thevoltage difference ΔVgd1 between the gate voltage Vg and the first drainvoltage Vd1, to ensure the accuracy of the written data signal when thescreen is refreshed.

Further, for the pixel circuits illustrated in FIGS. 1-4 , the voltagedifference ΔVgd1 between the gate 101 and the first drain 103 may oftenbe set within 2V. The voltage difference ΔVgd1 may be substantiallysmall, and the electric field strength may be substantially small, whichmay not cause a significant interference to the data signal when thescreen is refreshed. Therefore, in one embodiment, through setting0≤V0≤2V, it may be ensured that ΔVgd1 may be within a substantiallysmall voltage range, thereby improving the accuracy of written datasignal when the screen is refreshed to ensure the display effect. Undersuch premise, V0 may be further reduced to a range of 0≤V0≤1.5V,0≤V0≤1V, and 0≤V0≤0.5V, etc. Specifically, V0 may be one of 2V, 1.8V,1.5V, 1.2V, 1.0V, 0.8V, 0.6V, 0.4V, 0.2V, and 0V. In practicalapplications, a reasonable V0 value may be selected according to thespecific situation.

FIG. 8 illustrates a schematic diagram of a pixel circuit of anotherdisplay panel consistent with disclosed embodiments of the presentdisclosure; FIG. 9 illustrates a schematic diagram of a pixel circuit ofanother display panel consistent with disclosed embodiments of thepresent disclosure; and FIG. 10 illustrates a schematic cross-sectionalview of another driving transistor consistent with disclosed embodimentsof the present disclosure. Referring to FIGS. 8-10, the source 102 ofthe driving transistor T0 may include a first source 1021 and a secondsource 1022. A third driving portion T03 may be disposed between thefirst source 1021 and the second source 1022, and a length of a channelregion of the third driving portion T03 may be L3. The data-writingmodule 11 may be connected to the second source 1022, and thecompensation module 13 may be connected between the gate 101 and thefirst drain 103.

The foregoing embodiments may illustrate the processing methods when oneof ΔVsg and ΔVgd2 is greater than the other one and the voltagedifference is large to a certain extent. On such basis, the presentembodiment may further consider that the driving transistor may meet oneor more of following conditions: ΔVs2g=|Vs2−Vg|≤V0, where ΔVs2g may bethe voltage difference between the second source 1022 and the gate 101,and ΔVgd1=|Vg−Vd1|≤V0, where ΔVgd1 may be the voltage difference betweenthe first drain 103 and the gate 101. Then, the first driving portionT01 may participate in the data-writing stage, and the second drivingportion T02 and the third driving portion T03 with a substantially largevoltage difference may not participate in the data-writing stage.Therefore, the first driving portion T01 may have a substantially smallvoltage difference, which may improve the accuracy of the written datasignal as much as possible, and may avoid the problem of brightnessflickering when refreshing the screen.

In view of this, if ΔVs2g≤V0 is required,L3/(L1+L2)≥ΔVs1d2/(ΔVgd2+V0)−1, and 0≤V0≤ΔVs1g×½, whereΔVs1d2=|Vs1−Vd2|. In view of this, L1+L2 may be regarded as one piece,and then according to the above analysis process, such formula may beobtained. If ΔVgd1≤V0 is required, L2/(L1+L3)≥ΔVs1d2/(ΔVs1g+V0)−1, and0≤V0≤ΔVgd2×½, where ΔVs1d2=|Vs1−Vd2|, and ΔVs1g=|Vs1−Vg|. In view ofthis, L3+L1 may be regarded as one piece, and then according to theabove analysis process, such formula may be obtained. It should be notedthat FIG. 10 may merely exemplarily illustrate the intensity of theelectric field and the density of the electric field lines, and thedirections of the arrows may be adjusted according to specificimplementation.

Optionally, on the basis of the foregoing description, when ΔVs2g≤V1 andΔVgd1≤V1, the above two conditions may need to be met at the same time,and then L3/(L1+L2)≥ΔVs1d2/(ΔVgd2+V1)−1 andL2/(L1+L3)≥ΔVs1d2/(ΔVs1g+V1)−1 may be obtained, where V1 may be set to acertain value, which may facilitate the unified limitation of ΔVs2g andΔVgd1. According to the above description, when 0≤V1≤2V, a substantiallylarge voltage difference may be prevented from being generated betweenthe gate 101 and the second source 1022, and between the gate 101 andthe first drain 103, which may make the threshold voltage of the firstdriving portion T01 substantially stable, to fully avoid the flickeringproblem when refreshing the screen. Under such premise, V1 may befurther reduced to a range of 0≤V1≤1.5V, 0≤V1≤1V, and 0≤V1≤0.5V, etc.Specifically, V1 may be one of 2V, 1.8V, 1.5V, 1.2V, 1.0V, 0.8V, 0.6V,0.4V, 0.2V, and 0V. In practical applications, a reasonable V1 value maybe selected according to the specific situation.

The relationship between the lengths of the channel regions of the firstdriving portion T01, the second driving portion T02, and the thirddriving portion T03 and the related voltage differences may be describedabove. The structure of the driving transistor T0 may be described inthe following.

FIG. 11 illustrates a schematic top view of a driving transistorconsistent with disclosed embodiments of the present disclosure.Referring to FIG. 11 , a channel region 106 of the active layer 105 ofthe driving transistor T0 may include a first segment 1061, a secondsegment 1062, and a first site 200 disposed between the first segment1061 and the second segment 1062. The first drain 103 may be connectedto the first site 200, the first segment 1061 may be located in thefirst driving portion T01, and the second segment 1062 may be located inthe second driving portion T02. The gate 101 may include a first sidesurface 1011, and the first side surface 1011 may be a side surface ofthe gate 101 closest to the first site 200. At least a partial region ofthe first segment 1061 may have a distance away from the first sidesurface 1011 of the gate 101 greater than the distance between the firstsite 200 and the first side surface 1011. Alternatively, At least apartial region of the second segment 1062 may have a distance away fromthe first side surface 1011 of the gate 101 greater than the distancebetween the first site 200 and the first side surface 1011.

In the present disclosure, the setting of the first drain 103 may needto consider ΔVgd1, and ΔVgd1 may be related to the ratio of L1 over L2.In other words, the change of L1 or L2 may cause the change of ΔVgd1. Asdescribed above, both L1 and L2 may be designed according to certainrequirements. Therefore, to avoid unnecessary voltage change when thefirst site 200 is connected to the first drain 103, the length of thechannel region between the first site 200 and the first drain 103 mayneed to be sufficiently small, and the channel region may even not needto be disposed between the first site 200 and the first drain 103.

In view of this, the first site 200 may need to be extended beyond atleast one side of the gate 101, or may at least be extended very closeto a side surface of the gate 101, and such side surface may be definedas the first side surface 1011. In view of this, the distance betweenthe first site 200 and the first side surface 1011 may be zero, or maybe sufficiently small to be facilitated to be connected to the firstdrain 103. The first site 200 may be located between the first segment1061 and the second segment 1062. The first segment 1061 and the secondsegment 1062 may need to have lengths L1 and L2, respectively, and thechannel region 106 may overlap the gate. Therefore, to ensure thelengths of L1 and L2, at least one of the first segment 1061 and thesecond segment 1062 may need to be wound away from the first sidesurface 1011. After the lengths L1 and L2, at least one of the firstsegment 1061 and the second segment 1062 may be wound out of thecoverage of the gate 101. Especially, to consider the process factors,when the gate 101 is made into a rectangle, such design may be verynecessary. FIG. 11 illustrates a case where at least a portion of thesecond segment 1062 may have a distance away from the first side surface1011 greater than the distance between the first site 200 and the firstside surface 1011. In certain embodiments, at least a portion of thefirst segment 1061 may have a distance away from the first side surface1011 greater than the distance between the first site 200 and the firstside surface 1011.

In addition, optionally, in one embodiment, the gate 101 may furtherinclude a second side surface 1012. The second side surface 1012 may beconnected with the first side surface 1011, and the first side surface1011 and the second side surface 1012 may be two side surfaces of thegate 101 closet to the first site 200. At least a partial region of thefirst segment 1061 may have a distance away from the first side surface1011 of the gate 101 greater than the distance between the first site200 and the first side surface 1011, and/or at least a partial region ofthe second segment 1062 may have a distance away from the second sidesurface 1012 of the gate 101 greater than the distance between the firstsite 200 and the second side surface 1012.

Referring to FIG. 11 , the first side surface 1011 and the second sidesurface 1012 may be two side surfaces of the gate 101 closet to thefirst site 200. As described above, to ensure the accuracy of thevoltage of the first drain 103, the first site 200 may need to besufficiently close to the side surface of the gate 101 to facilitate theextraction of the first drain 103. However, on the other hand, thelengths of the first segment 1061 and the second segment 1062 may needto be ensured. Therefore, at least one of the first segment 1061 thesecond segment 1062 may need to be detoured, or both of the firstsegment 1061 the second segment 1062 may need to be detoured. Therefore,the distance between at least a partial region of the first segment 1061and the first side surface 1011 of the gate 101 may be greater than thedistance between the first site 200 and the first side surface 1011,and/or the distance between at least a partial region of the secondsegment 1062 and the second side surface 1012 of the gate 101 may begreater than the distance between the first site 200 and the second sidesurface 1012.

FIG. 12 illustrates a schematic top view of another driving transistorconsistent with disclosed embodiments of the present disclosure. Inaddition, optionally, referring to FIG. 12 , the first site 200 may notoverlap the gate 101. In view of this, the first site 200 may notconstitute a portion of the channel region, and may be connected to thefirst drain 103 after being extended, which may have little influence onthe voltage of the first drain 103, and may facilitate to the divisionof the first driving portion T01 and the second driving portion T02according to the voltage.

Optionally, referring to FIG. 11 , the first site 200 may at leastpartially overlap the gate 101. An auxiliary channel region 201 may bedisposed between the first site 200 and the first drain 103. Theauxiliary channel region 201 may have a length of L0, where0≤L0≤V0×(L1+L2)/(10×Vsd2). In one embodiment, as described above, thevoltage value of the first drain 103 may be obtained throughcomprehensive calculation. Therefore, the voltage loss may need to be assmall as possible when the first site 200 is connected to the firstdrain 103. If the first site 200 is disposed outside of the gate 101, inother words, if the first site 200 does not overlap the gate 101, theoverall area of the active layer 105 and the gate 101 on the panel mayincrease, which may not facilitate to improve the PPI of the panel.

Therefore, in some cases, the first site 200 may be set to at leastpartially overlap the gate, to save the total area occupied by theactive layer 105 and the gate 101. In view of this, to avoid voltageloss through the auxiliary channel region 201 when the first site 200 isconnected to the first drain 103, the length of the auxiliary channelregion 201 may need to be reduced as much as possible. According to theabove calculation, in the light-emitting stage, the voltage of the firstsite 200 may be Vd1. When the voltage of the first site 200 istransmitted to the first drain 103, assuming that the generated error isΔV1, the voltage of the first drain 103 may be Vd1′=Vd1±ΔV1. In thepresent disclosure, ΔVgd1≤V0. To ensure the voltage of the first drain103, ΔVgd1′≤V0, in other words, |Vg−Vd|±ΔV1|≤V0 and ΔVgd1±ΔV1≤V0. WhenΔV1/V0≤ 1/10, in other words, when ΔV1 is at least within the range ofone-tenth of V0, the auxiliary channel region 201 may have lessinfluence on the voltage of the first drain 103. On such basis, ΔV1/V0≤1/10, ΔV1/V0≤ 1/15, ΔV1/V0≤ 1/20, ΔV1/V0≤ 1/30, etc., may be furtherdefined, to fully ensure the accuracy of the voltage of the first drain103, and to ensure that the voltage between the gate 101 and the firstdrain 103 may be less than V0.

In view of this, because L0/L1≈ΔV1/ΔVsd1 and ΔV1/ΔVsd1≤V0× 1/10/ΔVsd1,then L0/L1≤V0× 1/10/ΔVsd1. Because ΔVsd1≈ΔVsd2×L1/(L1+L2), thenL0/L1≤V0× 1/10×(L1+L2)/L1/ΔVsd2, therefore 0≤L0≤V0×(L1+L2)/(10×Vsd2).

When L0 satisfies such condition, the auxiliary channel region 201 maybe prevented from affecting the voltage of the first drain 103 and ΔVgd1as much as possible. On such basis, 0≤L0≤V0×(L1+L2)/(15×Vsd2),0≤L0≤V0×(L1+L2)/(20×Vsd2) and 0≤L0≤V0×(L1+L2)/(30×Vsd2), etc., which maybe determined according to specific situations.

In addition, as described above, V0≤⅔×ΔVsd2×½=⅓ ΔVsd2, and0≤L0≤V0×(L1+L2)/(10×Vsd2), therefore 0≤L0≤(L1+L2)/30, which may ensurethe accuracy of the voltage of the first drain 103 and ΔVgd1.

In addition, in one embodiment, optionally, referring to FIGS. 11-12 ,the data-writing module 11 may be connected to the source 102, and thecompensation module 13 may be connected between the gate 101 and thefirst drain 103. The channel region of the first driving portion T01 mayhave a width smaller than the channel region of the second drivingportion T02.

In another embodiment, the data-writing module 11 may be connected tothe first drain 103, and the compensation module 13 may be connectedbetween the gate 101 and the second drain 104. The channel region of thefirst driving portion T01 may have a width greater than the channelregion of the second driving portion T02.

The width of a portion of the channel region participating in thedata-writing stage may be smaller than the width of a portion of thechannel region not participating in the data-writing stage. When thelength of the channel region and the electric field strength are fixed,the larger the width of the channel region, the larger the area, and thesmaller the electric field strength per unit area, i.e., the smaller theelectric field density. The deviation of the threshold voltage of thedriving transistor may be related to the electric field strength perunit area to certain extent. When the electric field strength betweenthe gate and the second drain or between the gate and the source issubstantially large, the deviation of the threshold voltage may besubstantially serious. Therefore, in one embodiment, the channel regionof the driving portion that does not participate in the data-writingstage may be appropriately widened, which may facilitate to reduce thedeviation of the threshold voltage. Therefore, when the first drivingportion T01 participates in the data-writing stage and the seconddriving portion T02 does not participate in the data-writing stage, thewidth of the channel region of the second driving portion T02 may beappropriately widened. When the first driving portion T01 does notparticipate in the data-writing stage and the second driving portion T02participates in the data-writing stage, the width of the channel regionof the first driving portion T01 may be appropriately widened.

Referring to FIGS. 1-12 , in one embodiment, one end of the data-writingmodule 11 may be connected to the data signal terminal for receiving thedata signal Vdata, the other end of the data-writing module 11 may beconnected to the driving module 12, and the control terminal of thedata-writing module 11 may be connected to the first scanning signalline S1 for receiving the first scanning signal. One end of thecompensation module 13 may be connected to the gate 101 of the drivingtransistor T0, the other end of the compensation module 13 may beconnected to the first drain 103 or the second drain 104 of the drivingtransistor T0, and the control terminal of the compensation module 13may be connected to the second scanning signal line S2 for receiving thesecond scanning signal. Optionally, the data-writing module 11 mayinclude a first transistor T1. A source of the first transistor T1 maybe connected to the data signal terminal, a drain of the firsttransistor T1 may be connected to the driving transistor T0, and a gateof the first transistor T1 may be connected to the first scanning signalline S1.

In addition, in one embodiment, the pixel circuit may further include alight-emitting control module 14. The light-emitting control module 14may selectively allow the light-emitting element 20 to enter thelight-emitting stage. The light-emitting control module 14 may include afirst light-emitting control module 141 and a second light-emittingcontrol module 142. One end of the first light-emitting control module141 may be connected to the first power signal terminal for receivingthe first power signal PVDD, the other end of the first light-emittingcontrol module 141 may be connected to the driving module 12, and thecontrol terminal of the first light-emitting control module 141 may beconnected to the light-emitting control signal line for receiving alight-emitting control signal EM. One end of the second light-emittingcontrol module 142 may be connected to the driving module 12, the otherend of the second light-emitting control module 142 may be connected tothe light-emitting element 20, and the control terminal of the secondlight-emitting control module 142 may be connected to the light-emittingcontrol signal line for receiving a light-emitting control signal EM.

The light-emitting control signal may be collectively referred to as EM.In one embodiment, the light-emitting control signal EM received by thefirst light-emitting module 141 may be the same as the light-emittingcontrol signal EM received by the second light-emitting module 142. Incertain embodiments, the first light-emitting control signal EM receivedby the first light-emitting module 141 may be different from thelight-emitting control signal EM received by the second light-emittingmodule 142. The first light-emitting control module 141 may include athird transistor T3. A source of the third transistor T3 may beconnected to the first power signal terminal, a drain of the thirdtransistor T3 may be connected to the driving transistor T0, and a gateof the third transistor T3 may be connected to the light-emittingcontrol signal line. The second light-emitting module 142 may include afourth transistors T4. A source of the fourth transistor T4 may beconnected to the driving transistor T0, a drain of the fourth transistorT4 may be connected to the light-emitting element 20, and a gate of thefourth transistor T4 may be connected to the light-emitting controlsignal line.

In the data-writing stage, the first scanning signal S1 may control thedata-writing module 11 to be turned on, and the data signal Vdata may bewritten into the source 102 (node N2) of the driving transistor T0through the data-writing module 11. The driving transistor T0 may beturned on, and the data signal Vdata may be written into the first drain103 (node N3) through the first driving portion T01. The second scanningsignal S2 may control the compensation module 13 to be turned on, andthe data signal Vdata may be written into the gate 101 (node N1) of thedriving transistor T0 through the compensation module 13. In thelight-emitting stage of the light-emitting element 20, thelight-emitting control signal EM may control the light-emitting module14 to be turned on, the driving transistor T0 may be turned on, and thedriving transistor T0 may generate a driving current to control thelight-emitting element 20 to emit light.

In addition, referring to FIGS. 1-12 , in one embodiment, the pixelcircuit 10 may further include an initialization module 15 and a resetmodule 16. One end of the initialization module 15 may be connected toan initialization signal terminal for receiving an initialization signalVini, the other end of the initialization module 15 may be connected tothe light-emitting element 20, and a control terminal of theinitialization module 15 may be connected to a fourth scanning line S4for receiving a fourth scanning signal. The initialization module 15 maybe configured to provide the initialization signal Vini to thelight-emitting element 20 in an initialization stage, to initialize thevoltage of the light-emitting element 20. The initialization module 15may include a fifth transistor T5. A source of the fifth transistor T5may be connected to the initialization signal terminal, a drain of thefifth transistor T5 may be connected to the light-emitting element 20,and a gate of the fifth transistor T5 may be connected to the fourthscanning signal line S4.

In one embodiment, the connection mode of the reset module 16 may beshown in FIG. 1 . One end of the reset module 16 may be connected to areset signal terminal for receiving a reset signal Vref, the other endof the reset module 16 may be connected to the gate 101 (node N1) of thedriving transistor T0, and a control terminal of the reset module 16 maybe connected to the third scanning signal line S3 for receiving thethird scanning signal. In the reset stage, the third scanning signalline S3 may control the reset module 16 to be turned on. The resetmodule 16 may provide a reset signal for the gate 101 of the drivingtransistor T0. The reset module 16 may include a sixth transistor T6. Asource of the sixth transistor T6 may be connected to the reset signalterminal, a drain of the sixth transistor T6 may be connected to thegate of the driving transistor T0, and a gate of the sixth transistor T6may be connected to the second scanning signal line S2.

In another embodiment, the connection mode of the reset module 16 may beshown in FIG. 2 . One end of the reset module 16 may be connected to thereset signal terminal for receiving the reset signal Vref, the other endof the reset module 16 may be connected to the first drain 103 (nodeN3), and the control terminal of the reset module 16 may be connected toa third scanning signal line S3 for receiving the third scanning signal.In the reset stage, the third scanning signal line S3 may control thereset module 16 to be turned on, the second scanning signal line S2 maycontrol the compensation module 13 to be turned on, and the reset signalVref may be written into the gate of the driving transistor T0 to resetthe driving transistor T0. In view of this, the source of the sixthtransistor T6 may be connected to the reset signal terminal, the drainof the sixth transistor T6 may be connected to the first drain 103 (nodeN3) of the driving transistor, and the gate of the sixth transistor T6may be connected to the third scanning signal line S3.

FIG. 13 illustrates a schematic diagram of a pixel circuit of anotherdisplay panel consistent with disclosed embodiments of the presentdisclosure; and FIG. 14 illustrates a schematic diagram of a pixelcircuit of another display panel consistent with disclosed embodimentsof the present disclosure. Optionally, referring to FIG. 13 and FIG. 14, the pixel circuit 10 may include a bias adjustment module 17. One endof the bias adjustment module 17 may be connected to a bias adjustmentsignal terminal for receiving a bias adjustment signal, the other end ofthe bias adjustment module 17 may be connected to the second drain 104(node N4) of the driving transistor T0, and the control terminal of thebias adjustment module 17 may be connected to a bias control signal lineS5 for receiving a bias control signal.

The working process of the pixel circuit may include a bias adjustmentstage. In the bias adjustment stage, the bias adjustment module 17 maybe turned on, the compensation module 13 may be turned off, and the biasadjustment signal may be transmitted to the second drain of the drivingtransistor T0. Because in the light-emitting stage, the voltagedifference between the second drain and the gate may be substantiallylarge, which may cause a substantially large electric field strength ofthe second driving portion. In one embodiment, to further improve suchproblem, the first bias adjustment module 17 may be connected to thesecond drain 104. The bias adjustment module 17 may be configured toprovide the bias adjustment signal to the second drain 104 in the biasadjustment stage, to reduce the voltage difference between the seconddrain and the gate, or to reverse the direction of the electric fieldbetween the second drain and the gate, to cancel out the problem ofdeviation of the threshold voltage of the driving transistor caused bythe electric field between the gate and the second drain during thelight-emitting stage.

Optionally, the bias adjustment module 17 may include a seventhtransistor T7. A source of the seventh transistor T7 may be connected tothe bias adjustment signal terminal, a drain of the seventh transistorT7 may be connected to the second drain 104 (node N4) of the drivingtransistor T0, and a gate of the seventh transistor T7 may be connectedto the bias control signal line S5.

Optionally, referring to FIG. 13 , the driving transistor T0 may be aPMOS transistor, and the bias adjustment signal may be a high voltagesignal VH. Because when the driving transistor is a PMOS transistor, inthe light-emitting stage, the voltage of the source of the drivingtransistor may often be substantially high, followed by the gate, andthen the second drain. The voltage of the second drain may often besubstantially low. To cancel out the deviation of the threshold voltagecaused by substantially low voltage of the second drain, the biasadjustment signal may be set to be the high voltage signal VH, to adjustthe strength of the electric field or even cancel out the electric fieldbetween the second drain and the gate as soon as possible in the biasadjustment stage.

Referring to FIG. 14 , the driving transistor T0 may be an NMOStransistor, and the bias adjustment signal may be a low voltage signalVL. Because when the driving transistor is an NMOS transistor, in thelight-emitting stage, the voltage of the source of the drivingtransistor may often be substantially low, followed by the gate, andthen the second drain. The voltage of the second drain may often besubstantially high. To cancel out the problem of the deviation of thethreshold voltage caused by the substantially high voltage of the seconddrain, the bias adjustment signal may be set to be the low voltagesignal VL, to adjust the strength of the electric field or even cancelout the electric field between the second drain and the gate as soon aspossible in the bias adjustment stage.

The present disclosure also provides a display panel. The display panelmay include a pixel circuit 10 and a light-emitting element 20. Thepixel circuit 10 may include a data-writing module 11, a driving module12, and a compensation module 13. The data-writing module 11 may beconfigured to selectively provide a data signal for the driving module12. The driving module 12 may be configured to provide a driving currentfor the light-emitting element 20, and the driving module 12 may includea driving transistor T0. The compensation module 13 may be configured tocompensate a threshold voltage of the driving transistor T0. The drivingtransistor T0 may include a source 102, a gate 101, an active layer 105,a first drain 103 and a second drain 104. A first driving portion T01may be disposed between the source 102 and the first drain 103, and asecond driving portion T02 may be disposed between the first drain 103and the second drain 104. A length of a channel region of the firstdriving portion T01 may be L1, and a length of a channel region of thesecond driving portion T02 may be L2.

In one embodiment, the data-writing module 11 may be connected to thesource 102, the compensation module 13 may be connected between the gate101 and the first drain 103, and L2/L1≥ΔVsd2/(ΔVsg+V0)−1 and 0≤V0≤2V; inanother embodiment, the data-writing module 11 may be connected to thefirst drain 103, the compensation module 13 may be connected between thegate 101 and the second drain 104, and L1/L2≥ΔVsd2/(ΔVgd2+V0)−1 and0≤V0≤2V, where ΔVsd2=|Vs−Vd2|, ΔVsg=|Vs−Vg|, and ΔVgd2=|Vg-Vd2|. In alight-emitting stage of the light-emitting element, Vs may be a voltageof the source of the driving transistor, Vd2 may be a voltage of thesecond drain of the driving transistor, and Vg may be a voltage of thegate of the driving transistor.

In one embodiment, 0≤V0≤2V may be defined. In other words, for the pixelcircuit in the present disclosure, when 0≤ΔVgd1≤2V, the strength ofelectric field between the gate 101 and the first drain 103 may bereduced to a certain extent, such that the deviation ΔV of the thresholdvoltage of the driving transistor T0 caused by the electric fieldbetween the gate 101 and the first drain 103 may be controlled within100 mV as much as possible, to avoid the deviation of the thresholdvoltage from significantly affecting the data-writing stage and to avoidflickering problem.

Under such premise, V0 may be further reduced within 0≤V0≤1.5V, 0≤V0≤1V,0≤V0≤0.5V, etc. Specifically, V0 may be one of 2V, 1.8V, 1.5V, 1.2V,1.0V, 0.8V, 0.6V, 0.4V, 0.2V, 0V, etc. A reasonable V0 value may beselected according to the specific situation in practical applications.

In addition, other implementation manners may refer to theabove-mentioned implementation manners, all of which may be appliedhere, and the details may not be repeated herein.

The present disclosure may also provide a display device. FIG. 15illustrates a schematic top view of a display device consistent withdisclosed embodiments of the present disclosure. Referring to FIG. 15 ,the display device 2 may include a display panel 1. The display panel 1may include a display panel in any one of the disclosed embodiments. Thedisplay device 2 may be one of a variety of display devices such as aTV, a notebook, a mobile phone, and a smart wearable display device,etc., which may not be limited by the present disclosure.

The display panel and display device in the present disclosure may atleast include following beneficial effects. In the present disclosure,the driving transistor may be divided into the first driving portion andthe second driving portion. In the data-writing stage, one of the firstdriving portion between the source and the first drain and the seconddriving portion between the first drain and the second drain may notparticipate in the data-writing stage. Further, the voltage differencebetween the first drain and the gate may be set within the range of V0,and V0 may often be set to be less than half of ΔVgd2 or half of ΔVsg.Therefore, the voltage difference between the first drain and the gatemay be reduced to within half of the original voltage difference betweenthe gate and the source or within half of the original voltagedifference between the gate and the second drain. Thus, the potentialdifference between the first drain or source and the gate may bereduced, thereby reducing the deviation of the threshold voltage of atleast one of the first driving portion and the second driving portion.One of the first driving portion and the second driving portion mayparticipate in the data-writing stage, while the other may notparticipate in the data-writing stage, such that the time lengthrequired to overcome the error when the display panel is refreshed maybe improved, the flickering problem may be reduced, and the displayeffect may be improved.

The description of the disclosed embodiments is provided to illustratethe present disclosure to those skilled in the art. Variousmodifications to these embodiments will be readily apparent to thoseskilled in the art, and the generic principles defined herein may beapplied to other embodiments without departing from the spirit or scopeof the disclosure. Thus, the present disclosure is not intended to belimited to the embodiments illustrated herein but is to be accorded thewidest scope consistent with the principles and novel features disclosedherein.

What is claimed is:
 1. A display panel, comprising: a pixel circuit anda light-emitting element, wherein: the pixel circuit includes adata-writing module, a driving module, and a compensation module; thedata-writing module is configured to selectively provide a data signalfor the driving module; the driving module includes a driving transistorand is configured to provide a driving current to the light-emittingelement; the compensation module is configured to compensate a thresholdvoltage of the driving transistor; the driving transistor includes asource, a gate, an active layer, a first drain and a second drain,wherein a first driving portion is arranged between the source and thefirst drain, and a second driving portion is arranged between the firstdrain and the second drain; a length of a channel region of the firstdriving portion is L1, and a length of a channel region of the seconddriving portion is L2; the data-writing module is connected to thesource of the driving transistor, the compensation module is connectedbetween the gate and the first drain of the driving transistor, andL2/L1≥0.5; or the data-writing module is connected to the first drain ofthe driving transistor, the compensation module is connected between thegate and the second drain of the driving transistor, and L1/L2≥0.5. 2.The display panel according to claim 1, wherein: the data writing moduleis connected to the source of the driving transistor, the compensationmodule is connected between the gate and the first drain of the drivingtransistor, and L2/L1≥2; or the data writing module is connected to thefirst drain of the driving transistor, the compensation module isconnected between the gate and the second drain of the drivingtransistor, and L1/L2≥2.
 3. The display panel according to claim 1,wherein: the data writing module is connected to the source, thecompensation module is connected between the gate and the first drain,and a width of the channel region of the first driving portion issmaller than a width of the channel region of the second drivingportion; or the data writing module is connected to the first drain, thecompensation module is connected between the gate and the second drain,and the width of the channel region of the first driving portion isgreater than the width of the channel region of the second drivingportion.
 4. The display panel according to claim 1, wherein: a channelregion of the active layer includes a first segment, a second segment,and a first site between the first segment and the second segment, thefirst drain is connected to the first site, the first segment is locatedat the first driving portion, and the second segment is located at thesecond driving portion, wherein: the gate includes a first side surface,the first side surface being a side surface of the gate closest to thefirst site, wherein: at least a partial region of the first segment hasa distance away from the first side surface of the gate greater than adistance between the first site and the first side surface; and/or atleast a partial region of the second segment has a distance away fromthe first side surface of the gate greater than the distance between thefirst site and the first side surface.
 5. The display panel according toclaim 4, wherein: the gate further includes a second side surface, thesecond side surface is connected to the first side surface, and thefirst side surface and the second side surface are two side surfaces ofthe gate closest to the first site, wherein: at least a partial regionof the first segment has a distance away from the second side surface ofthe gate greater than a distance between the first site and the secondside surface; and/or at least a partial region of the second segment hasa distance away from the second side surface of the gate greater thanthe distance between the first site and the second side surface.
 6. Thedisplay panel according to claim 4, wherein: the first site does notoverlap with the gate.
 7. The display panel according to claim 4,wherein: the first site at least partially overlaps with the gate, anauxiliary channel region is arranged between the first site and thefirst drain, a length of the auxiliary channel region is L0, wherein0≤L0≤(L1+L2)/30.
 8. The display panel according to claim 1, wherein: thedriving transistor is a PMOS transistor or an NMOS transistor.
 9. Adisplay device comprising a display panel including: a pixel circuit anda light-emitting element, wherein: the pixel circuit includes adata-writing module, a driving module, and a compensation module; thedata-writing module is configured to selectively provide a data signalfor the driving module; the driving module includes a driving transistorand is configured to provide a driving current to the light-emittingelement; the compensation module is configured to compensate a thresholdvoltage of the driving transistor; the driving transistor includes asource, a gate, an active layer, a first drain and a second drain,wherein a first driving portion is arranged between the source and thefirst drain, and a second driving portion is arranged between the firstdrain and the second drain; a length of a channel region of the firstdriving portion is L1, and a length of a channel region of the seconddriving portion is L2; the data-writing module is connected to thesource of the driving transistor, the compensation module is connectedbetween the gate and the first drain of the driving transistor, andL2/L1≥0.5; or the data-writing module is connected to the first drain ofthe driving transistor, the compensation module is connected between thegate and the second drain of the driving transistor, and L1/L2≥0.5. 10.The device according to claim 9, wherein: the data writing module isconnected to the source of the driving transistor, the compensationmodule is connected between the gate and the first drain of the drivingtransistor, and L2/L1≥2; or the data-writing module is connected to thefirst drain of the driving transistor, the compensation module isconnected between the gate and the second drain of the drivingtransistor, and L1/L2≥2.
 11. The device according to claim 9, wherein:the data writing module is connected to the source, the compensationmodule is connected between the gate and the first drain, and a width ofthe channel region of the first driving portion is smaller than a widthof the channel region of the second driving portion; or the data writingmodule is connected to the first drain, the compensation module isconnected between the gate and the second drain, and the width of thechannel region of the first driving portion is greater than the width ofthe channel region of the second driving portion.
 12. The deviceaccording to claim 9, wherein: a channel region of the active layerincludes a first segment, a second segment, and a first site between thefirst segment and the second segment, the first drain is connected tothe first site, the first segment is located at the first drivingportion, and the second segment is located at the second drivingportion, wherein: the gate includes a first side surface, the first sidesurface being a side surface of the gate closest to the first site,wherein: at least a partial region of the first segment has a distanceaway from the first side surface of the gate greater than a distancebetween the first site and the first side surface; and/or at least apartial region of the second segment has a distance away from the firstside surface of the gate greater than the distance between the firstsite and the first side surface.
 13. The device according to claim 12,wherein: the gate further includes a second side surface, the secondside surface is connected to the first side surface, and the first sidesurface and the second side surface are two side surfaces of the gateclosest to the first site, wherein: at least a partial region of thefirst segment has a distance away from the second side surface of thegate greater than a distance between the first site and the second sidesurface; and/or at least a partial region of the second segment has adistance away from the second side surface of the gate greater than thedistance between the first site and the second side surface.
 14. Thedevice according to claim 12, wherein: the first site does not overlapwith the gate.
 15. The device according to claim 12, wherein: the firstsite at least partially overlaps with the gate, an auxiliary channelregion is arranged between the first site and the first drain, a lengthof the auxiliary channel region is L0, wherein 0≤L0≤(L1+L2)/30.
 16. Thedevice according to claim 9, wherein: the driving transistor is a PMOStransistor or an NMOS transistor.